1. Field of Invention
The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for manufacturing local interconnects.
2. Description of Related Art
When the level of integration for integrated circuits is increased to such an extent that there is insufficient surface area on the wafer surface for laying the necessary interconnects, a design having two or more metallic layers is becoming common. This is especially true for rather sophisticated devices such as microprocessors. Sometimes four or Five metallic layers are required to finish the interconnection of devices in a microprocessor.
FIGS. 1A through 1D are cross-sectional views showing the progression of manufacturing steps in the production of local interconnect according to a conventional method. First, in FIG. 1A, a substrate 10 that has shallow trench isolation (STI) already formed in the substrate for defining a device region is provided. Furthermore, a gate oxide layer 12 has already been formed over the substrate 10, a first gate electrode 13 and a second gate electrode 14 has already been formed in the device region above the gate oxide layer 12, and spacers 15 has already formed on the sidewalls of the first and the second gate electrodes 13 and 14, respectively. The first gate electrode 13 and the second gate electrode 14 are composed of doped polysilicon, and the spacers are composed of silicon dioxide.
Next, as shown in FIG. 1B, a self-aligned silicide processing operation is performed. For example, a magnetron DC sputtering method is used to deposit a layer of metal such as titanium (Ti) over the first gate electrode 13, the second gate electrode 14 and the gate oxide layer 12. The deposited titanium layer preferably has a thickness of between 200 .ANG. to 1000 .ANG.. In the subsequent step, heating to a high temperature, the titanium layer is made to react with the first gate electrode 13, the second gate electrode 14 and the gate oxide layer 12 to form metal suicide layers 16. This metal silicide layers 16 are titanium suicide layers, for example. After that, unreacted and residual metallic material is removed.
Next, as shown in FIG. 1C, a reactive sputtering method is used to deposit a titanium nitride (TiN) layer 17a over the first gate electrode 13, the second gate electrode 14, the spacers 15 and the gate oxide layer 12. The titanium nitride layer 17a is formed by bombarding a titanium target with ions using a reactive gas mixture of argon and nitrogen The titanium sputtered out from the target due to ion bombardment reacts with the nitrogen atoms in the plasma to form the titanium nitride layer 17a. Thereafter, a layer of photoresist 18 is formed over the second gate electrode 14 and covers half of the surface between the first gate electrode 13 and the second gate electrode 14 above the gate oxide layer 12.
Next, as shown in FIG. 1D, the titanium nitride layer 17a not covered by a photoresist layer 18 is etched away to form a titanium nitride layer 17b.
Finally, subsequent processes, such as the removal of the photoresist layer 18, are performed to complete the fabrication of local interconnect. These subsequent processes are familiar to those skill in the art, and their detailed description is therefore omitted.
In the above conventional method of fabricating local interconnects, a rather complicated processing sequence is followed. The processing steps include titanium nitride deposition, patterning and etching. Hence, great differences in height levels can be produced on the wafer surface, which may adversely affect subsequent processing operations.
In light of the foregoing, there is a need in the art to provide a better method for manufacturing local interconnects.